1. Field of the Invention
This invention relates to integrated circuits, and more particularly, to methods for revealing speedpaths during the debugging of integrated circuits.
2. Description of the Related Art
One objective of microprocessor designers is to increase the clock speed at which a given processor design can operate. Characterization tests may be run to quantify the speed-limiting aspects of a microprocessor design. The circuits that limit the operating clock speed may then be re-designed, resulting in a new revision of the processor that may operate at the desired clock speed.
In order to increase the clock speed at which a processor (or other type of integrated circuit) operates, those areas of the design that prevent operating at a higher speed must be determined. Such areas may be identified by testing for failures associated with what are known as “speedpaths”. A speedpath-induced failure (hereafter ‘SIF’) is known as a failure that occurs when operating the processor at a frequency that would otherwise not fail when operating the processor at a lower frequency. A SIF occurs when data is unable to propagate through the combinational logic from one storage element (e.g. flip-flop) to the next within a given clock period. If the data is unable to reach the next storage element within the given clock period, incorrect data is forwarded to other portions of the processor, causing a failure. The propagation delay could be caused by an excessive amount of logic between storage elements or parasitic parameters in the data path inhibiting the propagation of the data. The top data paths that define the minimum clock period that can be used without causing a SIF are known as speedpaths.
One type of testing for SIFs involves the inputting to a device under test one or more test patterns over several iterations while increasing the clock speed for each iteration until the part fails. A first SIF resulting from testing of this type is known as a first order SIF. In some cases, testing may be terminated after finding a first order SIF, since any processor operation that occurs subsequent to the failure corresponding to the first order SIF is potentially corrupted by the first order speedpath.
During tests such as that described above, it may be desirable to find additional (or higher order) SIFs. This may be accomplished by momentarily slowing down the clock speed in order to mask lower order SIFs (sometimes referred to as “cycle stretching”). For example, assume a given test pattern includes 10,000 clock cycles and a fault corresponding to a first order speed path occurs during the 9000th clock cycle. In such a case, the first order SIF may be masked by slowing the clock down at the 9000th clock cycle to a frequency at which the failure does not occur. After the 9000th clock cycle, testing at the normal clock frequency may be resumed until the next failure occurs, which corresponds to a second order SIF. The process may be repeated to mask the first and second order SIFs in order to find a third order speedpath, and may be repeated for higher order SIFs as well.
One drawback to such testing is that it is difficult to obtain certain types of data (e.g., logic values) for SIFs higher than first order. For first order SIFs, internal data may be captured by what is known as a scan dump. A scan dump involves capturing logic values into a scan chain. A scan chain includes a plurality of scan elements. Logic values captured in a scan chain may be serially shifted out of the chain for observation. Both cycle stretching to mask lower order speedpaths and scan dumping involve clock manipulation. As noted above, cycle stretching involves changing the clock frequency for one or more cycles. Various embodiments of scan dumping require the clock to be completely stopped. Combining these techniques may be difficult, and thus it is often times only practical to perform scan dumping for a first order speedpath. However, data from a scan dump may be required in order to determine what is needed to correct problems that may be associated with any higher order speedpaths that prevent the processor from operating at higher clock speeds. Thus, a new silicon revision may be required for correcting each speedpath that is higher than the first order speedpath. The requirement of a new silicon revision in order to correct each speedpath may significantly increase the amount of time and money spent in designing the processor to operate at a higher clock speed.